1. Field of the Invention
The present invention relates to a semiconductor apparatus, and more particularly to a driving circuit of a power device in which a malfunction is prevented from occurring due to a dv/dt transient signal.
2. Description of the Background Art
FIG. 8 shows the structure of a driving circuit 100 of a power device according to the prior art. In FIG. 8, power devices 17 and 18 such as IGBTs (insulated gate bipolar transistors) are Totem-pole connected between a source potential VDD and a ground potential GND so that a half bridge type power device 19 is formed. Free-wheel diodes D1 and D2 are connected to the power devices 17 and 18 in antiparallel. A load (an inductive load such as a motor) 21 is connected to a node N1 of the power devices 17 and 18.
In FIG. 8, when the potential of the node N1 of the power devices 17 and 18 acts as a reference potential, the power device 17 performs switching operation between the reference potential and the source potential VDD supplied from a power source 20. The power device 17 will be hereinafter referred to as a high potential side power device.
When the ground potential acts as a reference potential, the power device 18 performs switching operation between the reference potential and the potential of the node N1. The power device 18 will be hereinafter referred to as a low potential side power device.
Accordingly, the driving circuit 100 of the power device shown in FIG. 8 is divided into a high potential side power device driving circuit HD and a low potential side power device driving circuit LD. Since the low potential side power device driving circuit LD is hardly related to the present invention, the description will be omitted.
The structure of the high potential side power device will be described below. Two outputs of a pulse generating circuit 1 are connected to the gate electrodes of high breakdown voltage field effect transistors (hereinafter referred to as HNMOS transistors) 2 and 3 which act as level shift transistors. The pulse generating circuit 1 generates pulse-shaped ON and OFF signals in response to an input signal sent from a microcomputer or the like which is provided on the outside. The drain electrodes of the HNMOS transistors 2 and 3 are connected to the first ends of resistors 4 and 5 and to the inputs of inverter circuits 6 and 7 respectively.
The outputs of the inverter circuits 6 and 7 are connected to the reset and set inputs of a non-inverted input type flip-flop circuit 10. The Q output of the flip-flop circuit 10 is connected to the gate electrode of an NMOS transistor 12 and to the input of an inverter circuit 11. The output of the inverter circuit 11 is connected to the gate electrode of an NMOS transistor 13.
The second ends of the resistors 4 and 5 are connected to the drain electrode side of the NMOS transistor 12, that is, the positive potential output of a high potential side power source 16. The source electrode of the NMOS transistor 13, that is, the negative potential output of the high potential side power source 16 is connected to the anodes of diodes 8 and 9. The cathodes of the diodes 8 and 9 are connected to the source electrodes of the HNMOS transistors 2 and 3 respectively.
Referring to the high potential side power device driving circuit HD, a fast dv/dt transient signal is generated on a line (hereinafter referred to as a line L1) which is provided from the node N1 to the anodes of the diodes 8 and 9 depending on the switching state of the half bridge type power device 19. Since a parasitic electrostatic capacity C is present between the drain-source of the HNMOS transistors 2 and 3, a current (hereinafter referred to as a dv/dt current) which is obtained by integration of the parasitic electrostatic capacity C and the dv/dt transient signal flows to the HNMOS transistors 2 and 3 at the same time.
The dv/dt current which flows to the HNMOS transistors 2 and 3 has the same level as that of a current which flows during normal switching. Consequently, a voltage drop occurs to the resistors 4 and 5 at the same time so that a "H" signal is sent to the set and reset inputs of the flip-flop circuit 10 simultaneously. In general, it is prohibited that the "H" signal is input to the set and reset inputs of the non-inverted input type flip-flop circuit at the same time. The reason is that unpredictable operation, that is, a malfunction is caused.
In order to prevent such a malfunction from occurring, it is required that the resistance values of the resistors 4 and 5 and the ON-state resistances of the HNMOS transistors 2 and 3 should be set with very high precision in such a manner that the voltage drop of the resistors 4 and 5 caused by the dv/dt transient signal can be distinguished from the voltage drop caused by a signal sent from the pulse generating circuit 1. Consequently, the ability to prevent the malfunction is limited.
A driving circuit 100A of the power device in which a filter circuit using a resistor and a capacitor or a capacity component is added to the first stage of the input of the flip-flop circuit 10 has been devised. The high potential side power device driving circuit HD1 of the driving circuit 100A of the power device will be described below with reference to FIG. 9. The same reference numbers designate the same structure as that of the driving circuit 100 of the power device described above with reference to FIG. 8, and the same description will not be repeated.
In FIG. 9, a resistor 22 is inserted between the output of the inverter circuit 6 and the reset input of the flip-flop circuit 10, and a resistor 23 is inserted between the output of the inverter circuit 7 and the set input of the flip-flop circuit 10. A capacitor 24 is inserted between the line L1 and the reset input of the flip-flop circuit 10, and a capacitor 25 is inserted between the line L1 and the set input of the flip-flop circuit 10 so that a filter circuit 26 is formed.
The operation of the high potential side power device driving circuit HD1 will be described below with reference to FIG. 9.
When a dv/dt transient signal is applied to the line L1 depending on the switching state of the half bridge type power device 19, a dv/dt current flows to the HNMOS transistors 2 and 3 at the same time so that a voltage drop occurs to the resistors 4 and 5 simultaneously. Consequently, the "H" signal is output from the inverter circuits 6 and 7. However, the "H" signal is not input to the flip-flop circuit 10 until a predetermined time (hereinafter referred to as a lag time) that is set by the time constant of a CR filter (hereinafter referred to as an OFF side CR filter because it is connected to the HNMOS transistor 2 to which an OFF signal is input) formed by the capacitor 24 and the resistor 22 connected to the inverter circuit 6 and a predetermined time that is set by the time constant of a CR filter (hereinafter referred to as an ON side CR filter because it is connected to the HNMOS transistor 3 to which an ON signal is input) formed by the capacitor 25 and the resistor 23 connected to the inverter circuit 7 pass.
By setting the lag time greater than the application time for the dv/dt transient signal, the "H" signal generated by the dv/dt current is not sent to the flip-flop circuit 10 so that the malfunction of the flip-flop circuit 10 can be prevented from occurring.
On the other hand, the output signals of the inverter circuits 6 and 7 generated based on the ON and OFF signals output from the pulse generating circuit 1 are sent to the flip-flop circuit 10 by setting the pulse widths of the ON and OFF signals output from the pulse generating circuit 1 much greater than the application time for the dv/dt transient signal, that is, greater than the lag time caused by the filter circuit. Consequently, the flip-flop circuit 10 is normally operated.
Referring to the high potential side power device driving circuit HD according to the prior art described above, the resistance values of the resistors 4 and 5 and the ON-state resistances of the HNMOS transistors 2 and 3 are set in such a manner that the voltage drop of the resistors 4 and 5 caused by the dv/dt transient signal can be distinguished from the voltage drop caused by the signal sent from the pulse generating circuit 1, so that the malfunction can be prevented from occurring due to the dv/dt transient signal. However, setting should be performed with high precision. Accordingly, when a margin for the ability to prevent the malfunction for the change of the dv/dt transient signal is decreased and the dv/dt transient signal is increased, setting cannot be performed theoretically. Actually, a semiconductor apparatus has been developed in such a manner that the dv/dt transient signal is increased.
In the high potential side power device driving circuit HD1 according to the prior art, it is necessary to set the pulse widths of the ON and OFF signals output from the pulse generating circuit 1 much greater than the application time for the dv/dt transient signal. The switching operation of the power device is limited by the dv/dt transient signal, and the output signals of the inverter circuits 6 and 7 are sent to the flip-flop circuit 10 later by the lag time set by the filter circuit 26. Consequently, the response performance of the power device 17 is lowered. Accordingly, the driving circuit HD1 is nor suitable for the power device which requires high-speed operation.
Such operation will be described with reference to a timing charts shown in FIG. 10A to FIG. 10E. When the power device 17 is turned ON, the pulse generating circuit 1 outputs a "H" signal as an ON signal and a "L" signal as an OFF signal. The inverter circuit 7 outputs the "H" signal. The output of the ON side CR filter circuit which receives the "H" signal gradually rises until charges are filled in the capacitor 25. The output of the ON side CR filter circuit falls in the same manner. When the output of the ON side CR filter circuit completely rises, the "H" signal is output from the Q output of the flip-flop circuit 10.
When the power device 17 is turned OFF, the pulse generating circuit 1 outputs a "L" signal as an ON signal and a "H" signal as an OFF signal. Then, the inverter circuit 6 outputs the "H" signal. The output of the OFF side CR filter circuit which receives the "H" signal gradually rises until the capacitor 24 is charged. The output of the OFF side CR filter circuit falls in the same manner. When the output of the OFF side CR filter circuit completely rises, the "L" signal is output from the Q output of the flip-flop circuit 10.
Accordingly, the power device 17 is kept ON while the "H" signal is output from the Q output of the flip-flop circuit 10. The period is longer by the lag times of the ON and OFF side CR filter circuits as compared with the case where the filter circuit 26 is not provided.
If the dv/dt transient signal is applied, the dv/dt current flows to the HNMOS transistors 2 and 3 at the same time. A voltage drop occurs to the resistors 4 and 5 at the same time so that the "H" signal is output from the inverter circuits 6 and 7. While the dv/dt transient signal is applied, the capacitors 25 and 24 of the ON and OFF side CR filter circuits cannot be charged completely. For this reason, the outputs of the ON and OFF side CR filter circuits do not reach a level at which a malfunction occurs to the flip-flop circuit 10.
In order to set the lag time accurately, it is necessary to set the rated values of the resistors 22 and 23 and the capacitors 24 and 25 with high precision. In particular, in the case where the resistors and capacitors are used for an integrated circuit (IC), the temperature dependency of the rated value and a variation in rated value caused by manufacture should be considered. Hence, it is very hard to set the lag time accurately. In addition, the resistors and capacitors have great areas on the pattern of the integrated circuit. Consequently, integration cannot be enhanced due to the presence of the filter circuit 26.
The power device 17 is operated by the edge trigger of the pulse-shaped ON and OFF signals in order to confine power consumption to the minimum. The above problems are peculiar to a system for operating the power device 17 by the edge trigger of the pulse-shaped ON and OFF signals.